STM32 HSE unstable frequency

I'm trying to run my Nucleo f401re on 80mhz from HSE

int F4xxx::clockInit(int pllM, int pllN, int pllP, int pllQ)
{
    enableHse();

    //FLASH
    CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
    FLASH->ACR&= ~FLASH_ACR_LATENCY;
    FLASH->ACR |= FLASH_ACR_LATENCY_5WS | FLASH_ACR_ICEN | FLASH_ACR_DCEN|FLASH_ACR_PRFTEN;

    //set HSE as PLL source
    RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE;
    //
    RCC->CR &= ~(RCC_CR_PLLON); //disable PLL before changes
    //

    RCC->PLLCFGR = pllM|(pllN<<6)|(((pllP>>1)-1)<<16)|RCC_PLLCFGR_PLLSRC_HSE|(pllQ<<24);
    RCC->CR|=RCC_CR_PLLON;
    while(!(RCC->CR&RCC_CR_PLLRDY));

    RCC->CFGR &= ~(RCC_CFGR_HPRE);  //Prescaler 1
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //AHB = SYSCLK/1


    //APB2 Prescaler 2
    RCC->CFGR &= ~(RCC_CFGR_PPRE2);
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;  //APB2 /1

    RCC->CFGR &= ~(RCC_CFGR_PPRE1);
    RCC->CFGR|=RCC_CFGR_PPRE1_DIV1; // APB1 /2

    RCC->CFGR &= ~RCC_CFGR_SW; // reset SW0, SW1.
    RCC->CFGR |= RCC_CFGR_SW_PLL;
    RCC->CR|=RCC_CR_PLLON;

    while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_PLL); // wait for switching to PLL (while PLL is not used as system clock)

    // for power saving
    RCC->CR &= ~(RCC_CR_HSION);

    return 0;
}

void F4xxx::enableHse()
{
    // for control MCO2 (PC9): (freq=SYSCLK/5)
    RCC->AHB1ENR|=RCC_AHB1ENR_GPIOCEN;
    GPIOC->MODER&=~GPIO_MODER_MODE9;
    GPIOC->MODER|=GPIO_MODER_MODE9_1;
    GPIOC->OSPEEDR|=GPIO_OSPEEDER_OSPEEDR9;
    RCC->CFGR|=RCC_CFGR_MCO2PRE;

    RCC->CR |= (RCC_CR_HSEON); //Enable HSE
    while( !(RCC->CR & RCC_CR_HSERDY) ) {}; //ready to start HSE
}

and then call it like this:

f4.clockInit(8, 336, 2, 7);

But my logic analyzer show that the frequency is unstable

The peaks with level=1 have width^-1 = 16 mhz But the peaks with level=0 have width^-1 = 8 mhz and 5.33 mhz

What could cause such an unstable frequency?