如何在VHDL中将新行写入文件？

我想new line在输出文件中用字符分隔数据，但是以下代码导致错误“无法解决过程调用的重载”：

write(out_line, "\n"); 
write(out_line, ""); 
write(out_line, '');

我想如何使用它的示例代码：

ENTITY writer IS 
PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;

ARCHITECTURE arch OF writer IS
    SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
    TYPE state_type IS (init, write_file);
    SIGNAL state : state_type := init;
BEGIN
    PROCESS (clk, start)
        FILE out_file : text;
        VARIABLE out_line : line;
    BEGIN
       IF rising_edge(clk) THEN
           CASE state IS 
               WHEN init => 
                   IF start = '1' THEN
                       state <= write_file;
                   ELSE 
                       state <= init;
                   END IF;
               WHEN write_file =>
                   state => init;

                   FOR i IN 0 TO 10 LOOP
                       write(out_line, vect);
                       writeline(out_file, out_line);
                       -- write(out_line, "\n"); <-- 
                       -- write(out_line, ""); <-- 
                       -- write(out_line, ''); <-- None of these work
                       writeline(out_file, out_line); 
                   END LOOP;
           END CASE;
       END IF;
   END PROCESS;
END ARCHITECTURE;
               

所以我想知道，VHDL是否可能？如果是，怎么办？