How can I avoid circular dependency in my Makefile compiling obj file with g++ and gcc?

I tried to create a makefile for a project that use c++ and c. I need to compile those file in order to make de .o file, but when I compile using make I have circular dependency that is dropped.

I don't know why this error occurs as I tried to separate the building of .o files that comes from .c and .o files that comes froms .cpp files.

Here is my makefile :

SRC = $(wildcard *.c)
SRC++ = $(wildcard *.cpp)
OBJ = $(SRC++:.cpp=.o) $(SRC:.c=.o)
DEP = $(SRC:.c=.d) $(SRC++:.cpp=.d)

CC=gcc
CXX=g++

CFLAGS = -Wall
CXXFLAGS = -Wall

all: $(OBJ)

%.c : %.o
    $(CC) -c $(CFLAGS) $< -o $@  

%.cpp : %.o
    $(CXX) -c $(CXXFLAGS) $< -o $@  

# Clean the project
clean:
    @rm -f $(OBJ) $(DEP)

-include $(DEP)

Do you have any idea of what I am doing wrong ?