Using migen or chisel HDL languages on pynq FPGA boards

I am currently using the pynq-z2 FPGA eval board manufactured by TUL to design applications. It has a Processor+FPGA SoC Zynq7020 on it. The pynq python package allows us to interact with the PS and PL quite well via jupyter notebooks.

I wanted to know if we could write the verilog codes for the PL in the new languages like migen 1 and chisel on pynq supported boards. Currently I am writing VHDL/verilog files in Vivado and creating IPs and circuit design in PL.

More info about migen: https://m-labs.hk/migen/manual/introduction.html

More info about chisel: https://www.chisel-lang.org/chisel3/docs/introduction.html