计数器的输出未在Verilog仿真中显示为已初始化

为确保计数器正常运行，我在运行模拟时遇到了一些麻烦。我的柜台的代码是：

module counter(
    input clk, rst,
    output reg [16:0] counterout
    );
always @(posedge(clk), posedge(rst))
begin
     if (rst) counterout <= 0;
     else if (clk) counterout <= counterout + 1;
end
endmodule

和我的测试代码：

`timescale 1ns / 1ps
module testbench();

reg clock;
reg rst;
wire [16:0] out;

counter test(
    .clk(clock),
    .rst(rst),
    .counterout(out)
);

integer k = 0;

initial
begin
    rst = 0;
    clock = 0;
    #100 ;
    
    for(k = 0; k < 1000; k = k+1)
    begin
        #5 clock = clock + 1;
    end
    #5 $finish;
end
endmodule

不幸的是，当我运行仿真时，它显示的输出从未初始化。知道为什么吗？