Chisel PeekPokeTester中的Printf行为与同一RTL上的验证器不同

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在Chisel的象素中打印似乎会输出寄存器值的更新版本,这使相同的Chisel打印代码在Chisel后端和验证程序后端中的行为有所不同。

在使用Chisel后端时,打印似乎只是记录硬件对象的参考,但是在当前步骤的逻辑模拟之后执行打印,然后参考会以更新的值进行回复。

我搜索了凿子回购的问题和凿子用户组,但很少有关于此主题的讨论。

这是凿模板回购的自包含代码示例

package myrtl

import chisel3._
import chisel3.iotesters._

class Foo extends Module {

  val io = IO(new Bundle {
    val in = Input(UInt(32.W))
    val out = Output(UInt(32.W))
  })

  val v = Wire(UInt(32.W))
  when (v === 0.U) {
    printf(p"v $v\n")
  }

  val reg = RegInit(0.U(32.W))
  reg := io.in
  io.out := reg
  v := reg
}

class FooTester(dut: Foo) extends PeekPokeTester(dut) {
  poke(dut.io.in, 32)
  step(1)
}

object TestMain extends App {
  iotesters.Driver.execute(args, () => new Foo)(dut => new FooTester(dut))
}

注意的条件printf荒谬的是,通过启用打印v === 0.U但将其输出v为的值32

塞尔德里奇

我相信这是一个已报告的错误,其中的printf语句没有正确计算其依赖关系(并已修复)。

在过去的一年中,有许多重构可能是解决这个问题的原因:

您可以尝试切换到1.3-SNAPSHOT声呐类型并重新测试吗?

diff --git a/build.sbt b/build.sbt
index 6d18fe7..c13d44d 100644
--- a/build.sbt
+++ b/build.sbt
@@ -41,11 +41,10 @@ resolvers ++= Seq(

 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
 val defaultVersions = Map(
-  "chisel3" -> "3.1.+",
-  "chisel-iotesters" -> "[1.2.5,1.3.0["
+  "chisel-iotesters" -> "1.3-SNAPSHOT"
   )

-libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
+libraryDependencies ++= Seq("chisel-iotesters").map {
   dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }

 scalacOptions ++= scalacOptionsVersion(scalaVersion.value)

通过对的这些修改build.sbt,我可以看到不进行任何打印的预期行为。这与Verilator有所不同,Verilator在模拟开始之前似乎只有一张印刷品。使用1.3-SNAPSHOT

sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name treadle
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name treadle
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 408.8 ms
file loaded in 0.071117471 seconds, 15 symbols, 12 statements
[info] [0.001] SEED 1568033935603
test Foo Success: 0 tests passed in 6 cycles in 0.012474 seconds 481.00 Hz
[info] [0.003] RAN 1 CYCLES PASSED
[success] Total time: 2 s, completed Sep 9, 2019 8:58:56 AM

并且在使用verilator时(带有一些输出片段):

sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name verilator
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name verilator
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 440.6 ms
[info] [0.001] SEED 1568034082729
[info] [0.007] v          0
[info] [0.007]          0
Enabling waves..
Exit Code: 0
[info] [0.011] RAN 1 CYCLES PASSED
[success] Total time: 4 s, completed Sep 9, 2019 9:01:25 AM

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